The ion trap^[1] is currently a major candidate for quantum information process (QIP), serving as quantum memories, quantum gates, and nodes of quantum communication networks.^[2] Quantum bits based on trapped ions have many advantages, including exquisite coherence properties and high efficiency to be prepared, entangled, and measured. However, the remaining challenge is the scaling of trapped ions to tremendous quantum bits, which is necessary for realizing scale quantum processors.^[3]

The surface-electrode ion trap is an effective scaling approach due to its compatibility with the existing semiconductor process.^[4] Several main surface-electrode trap geometries, single-layer, double-layer, and quasi-double-layer, have been experimentally realized. Single-layer surface-electrode (SSE) traps are much more suitable for the silicon-based micro-fabrication technology, where all electrodes are laid in the same plane. Since the first SSE trap was fabricated by MIT,^[5] numbers of SSE traps^[6–11] have been fabricated and tested, with high-fidelity quantum bits preparation, detection, transportation, and gate operations.^[12–19] Double-layer surface-electrode (DSE) traps^[20–23] have a deeper potential trap than SSE traps, which can extend the life time of trapped ions remarkably.^[24,25] Therefore, although the fabrication process is complex, some researchers still attempt to develop DSE traps.^[26,27] Another surface-electrode trap, the quasi-double-layer surface-electrode (QSE) trap, has the construction characteristic of that in between SSE and DSE traps.^[28,29] After optimizing, the potential trap of QSE traps can be several times as deep as that of SSE traps, confirming that ions easily like a DSE trap. Moreover, the fabrication process of QSE traps is similar to that of SSE traps, which is much easier than that of DSE traps.

For all the traps above, to achieve a desired potential trap in the trap design process is critical for experiments. However, the widely used approach is always time consuming, which is to simulate the electric field with a finite element method (FEM) based software (i.e., Ansoft Maxwell or COMSOL). Moreover, the FEM simulation is also incapable of exhibiting the direct relationship between the geometry dimension and the critical trap parameters, such as the trap center and trap depth. To eliminate the problems above, House and Madsen et al. have respectively provided analytical models for SSE traps^[30] and DSE traps.^[31] Here, to provide insights in QSE traps design, this paper proposes a semi-analytical model for QSE traps. This model provides a fast and precise way in calculating trap parameters and designing the geometry of trap electrodes for desired fields. We have verified the proposed model against the FEM simulation. With this model, we have analyzed critical factors which determine the trap center and trap depth, and found the optimum geometry design for QSE traps. The remainder of this paper is organized as follows. In Section 2, we compare QSE traps with SSE and DSE traps and define geometry parameters for QSE traps. In Section 3, we propose the semi-analytical model for QSE traps and discuss insights provided by this model. Section 4 demonstrates that the model can describe QSE traps accurately through verification experiments. In Section 5, the model is applied to find the optimal geometries for the trap electrodes. Finally, Section 6 provides our conclusion.

In order to enhance the scalability of Paul traps, SSE and DSE traps have been implemented by mapping Paul traps to a flat surface as shown in Fig. 1. The trap depth is a key performance indicator for surface-electrode ion traps, which can be defined by the pseudopotential. The pseudopotential is defined as^[32]

Fig. 1.

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	Fig. 1. The mapping from Paul traps to SSE and DSE traps. In the mapping to SSE traps, the 3D structure of Paul traps is mounted on a single layer surface with geometry parameters including a and b. When mapping to DSE traps, this 3D structure is mounted on two layers with geometry parameters which are a and d.

There is a large difference in the trap depth among Paul, SSE, and DSE traps. Figure 2 shows the FEM simulation for the pseudopotential of these ion traps with the same characteristic size R = 100 μm and the optimum geometry design described above, where the trapped ion is ⁴⁰Ca⁺, the amplitude and frequency of the voltage applied to RF electrodes are 100 V and 10 MHz. The trap depths of these Paul, SSE, and DSE traps are respectively 167 eV, 0.3 eV, and 15.1 eV. The DSE trap has a 50 times deeper trap depth than the SSE trap, so the DSE trap can confine the ions more easily. Though the SSE trap has the shallowest trap, it is a popular way to achieve the ion trap QIP because of its simple fabrication process.

Fig. 2.

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	Fig. 2. The pseudopotential along the y axis. Results are derived from the FEM simulation. The pseudopotential along the y axis constructs a trap for trapping ions. The trap depth is various in different types of ion traps.

The QSE trap has a similar structure to the SSE trap, but RF and GND electrodes located in different planes. Compared with the SSE trap, fabricating a QSE trap is only required to add the process of etching, which is simpler than fabricating a DSE trap. Figure 3 shows the structure of a QSE trap and the pseudopotential above electrodes. As shown in Fig. 3(a), the pseudopotential has a saddle point above the trap center that connects the trap center with the region where the pseudopotential goes to zero as y → ∞, which is the easiest point for the ion to escape from the trap. The pseudopotential at this escape point represents the trap depth. Figure 3(b) is the top view of the QSE trap. Geometry parameters of the QSE trap include the width b, length l, and height d of RF electrodes, the distance between RF electrodes a, and the width of DC electrodes w. R = a is the characteristic size of QSE traps. When a = 100 μm, the deepest potential trap reaches about 7 eV (derived from the FEM simulation), which is 23 times as deep as that of the SSE trap with the same characteristic size.

Fig. 3.

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Fig. 3. The structure of a QSE trap and the pseudopotential above electrodes. (a) The cross-sectional view of the QSE trap. The ion is to be trapped in the potential trap near the center of the figure. The lowest energy path for the ion to escape the trap is through the saddle point in the pseudopotential directly above. The difference in pseudopotential between the center of the trap and this escape point represents the trap depth. (b) The top view of the QSE trap, which consists of five electrode rails, two DC electrodes, two RF electrodes, and one ground electrode. The origin point is illustrated above. The parameters a, b, d, l, and w define the dimensions of the electrodes.

Because the precise analytical model is hard to derive directly, we simplify the structure of the QSE trap with some assumptions as follows.

In fact, ion traps always have long electrodes, so assumption (I) is acceptable. Only the potential in the space y > 0 is considered in the semi-analytical model. In this space, the boundary condition is similar to that described in assumption (II). Assumption (III) is used to simplify the calculation of electric fields. We will add several additional factors to correct the error caused by assumption (III) in the following text. Some of the assumptions above have also been used in analyzing SSE traps^[30] and DSE traps,^[31] deducing analytical models whose accuracy has been confirmed. Moreover, the influences of assumptions (I) and (II) for surface-electrode ion traps have been found to be very small in realistic situations.^[33]

According to assumptions (I) and (III), the RF electrode can be considered as a wire with an infinite length. After conformal mapping as follows:

The linear charge density q can be obtained by the following method. Regarding the RF electrode and the y = −d plane as a parallel plate capacitor with distance d and different plate area, the charge on the surface of the y = −d plane mainly distributes in the corresponding region with width c. This parallel plate capacitor is equivalent to lots of small series capacitors with distance dy and the same plate area. The capacitance value of each small capacitor can be calculated by the formula of C(y) = ε₀S(y)/dy, where S(y) is the plate area of the parallel plate capacitor at y. By evaluating the integral of and solving C = ql/U, the expression of q can be obtained as

Equations (6), (7), and (10) compose the full semi-analytical model for QSE traps, which is capable of calculating critical parameters such as the trap center, the escape point, and the trap depth, directly. This model provides several insights in trap design listed as follows.

Insight 1 The trap center and the escape point are only related to the geometry dimension.

Insight 2 A large voltage and a small electrode are beneficial for a deep trap.

Insight 3 For a given characteristic size, we can find the optimum design of the relative dimension.

Insight 1 is useful in designing laser paths. When cooling ions for initialization or controlling ions for quantum computing or reading out the final state of ions, the trap center is the target location of applied lasers. For a given QSE trap, we can derive the target location from the model determined by the geometry factors including a, b, and d. Insight 2 indicates how to make the effort to improve the trap. One way to achieve a deep trap is to apply large voltage to electrodes. Thus, finding a way to improve the withstand capability of electrodes is of concern. Another way is to implement electrodes as small as possible, so long as technology allows. Insight 3 tells us that, for a determined characteristic size a, we can further improve the trap by finding the optimum design for the relative dimension α and β.

In the following verification experiments, the trapped ion is ⁴⁰Ca⁺ and the frequency of voltage Ω is 10 MHz. The relationship between the trap depth and factors such as U, a, α, and β is important for trap design. One part of the verification is to test the consistence of that relationship between the semi-analytical model and the FEM simulation. Figure 4 plots the trap depth with various U when characteristic size a sweeps from 50 μm to 150 μm. The lines represent the results derived from the semi-analytical model, and the points with different shapes show the results derived from the FEM simulation. As shown in Fig. 4, the analytical result agrees well with the simulation result. Figure 4 also exhibits that Insight 2 is correct.

Fig. 4.

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	Fig. 4. The trap depth of the QSE trap versus U and characteristic size a. U varies from 20 V to 180 V, and for each U, a is set to 50 μm, 100 μm or 150 μm.

Figure 5 plots the comparison between the trap depth derived from the semi-analytical model and that from the FEM simulation when the relative sizes α (= b/a) or β (= d/a) varying. The amplitude of the voltage is U = 100 V and the characteristic size is a = 100 μm. The trap depth climbs firstly and then declines with α increasing (see Fig. 5(a)), and it has a similar relationship with β (see Fig. 5(b)). The analytical result is identical with the simulation result as shown in Fig. 5, which proves that the semi-analytical model is accurate in expressing the relationship between the trap depth and relative sizes α and β.

Fig. 5.

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	Fig. 5. The trap depth of the QSE trap versus (a) α (= b/a) in the range of 0.05–2 and (b) β (= d/a) in the range of 0.1–3.

The semi-analytical model also provides the way to find the locations of the trap center and escape point as described in Eqs. (6) and (7). Figure 6 plots the pseudopotential along the y axis derived from κ_bκ_dψ(a/2,y,0) and the FEM simulation respectively when U = 50 V, U = 100 V, or U = 200 V. The lines represent the results of analysis and the points indicate the results of simulation. As shown in Fig. 6, both of analysis and simulation find the same locations of the trap center and escape point that are in agreement with Eqs. (6) and (7). Moreover, for a given ion trap, varying the factors (i.e., voltages as shown in Fig. 6) besides the geometry dimension has no influence on the trap center or the escape point. Therefore, as described in Insight 1, the trap center and the escape point are only related to the geometry dimension.

Fig. 6.

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	Fig. 6. The comparison of the pseudopotential along the y axis.

One purpose in the design for QSE traps is to find the geometry dimension of electrodes that makes the trap depth as deep as possible. According to Insight 3, when the characteristic size a is determined, the factors that influent the trap depth are relative sizes α and β, which determine values of width b and height d of RF electrodes. In order to find the optimum design of RF electrodes, we calculate the trap depth when both α and β are varying. Figure 7 shows the results derived from the semi-analytical model (solid lines) and the FEM simulation (dot lines). Both of them find the optimum design as α = 0.15 and β = 1.2. The trapping potential is weaker if the RF electrodes are chosen to be too narrow or too wide in width, as well as too low or too high in height.

Fig. 7.

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	Fig. 7. The trap depth of the QSE trap when both α and β are varying. Solid lines show the result derived from the semi-analytical model and dot lines indicate the result derived from the FEM simulation.

Another goal is to find the best dimension for the width w of the DC electrode, which should be chosen so that the field it creates has significant curvature everywhere along the ion transport path in the z dimension.^[34] Figure 8 shows the potential curvature in z axis with five different values for w. The RF electrodes design is α = 0.15 and β = 1.2. When w is relatively small (w/a = 0.5), the potential curvature at the trap center is also small and the electrode’s influence is relatively weak. If w is chosen to be very large (w/a = 2.5), the potential curvature is reduced near the center of the electrode in z. The location where the potential curvature equals to zero is of great concern. When w/a equals to 1.5 or 2.0, as w increases, a zero in the potential curvature approaches z = ± w/2, the edge of the electrode. This is an inconvenient place for it, since the neighboring electrode will also have a zero near the same edge. If the ion is to be shuttled across this point, large voltages may be needed since no electrode can contribute strongly to the potential curvature at that point. Therefore, in QSE traps design, a good choice for the width of the DC electrode is w = a.

Fig. 8.

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Fig. 8. The potential curvature in z dimension at the trap center with respect to z/w. For small w that w = 0.5a, the curvature is relatively small. For very large w that w = 2.5a, the curvature is reduced near the center of the segment. When w/a equals to 1.5 or 2.0, the potential curvature equals to zero at z = ±w/2, which is not good for ion transport. Thus, a good choice for the width is w = a.

In this paper, we have proposed a semi-analytical model for QSE traps, providing a fast and precise way in designing the geometry of trap electrodes to achieve desired fields. We make several reasonable assumptions to simplify the deduction of the model. Through conformal mapping, we calculate the electric field of the QSE trap, and then obtain locations of the trap center and escape point, and the expression of the trap depth, which compose the full semi-analytical model of QSE traps. To correct the error caused by the assumption, we add two factors to the model. The verification experiments prove that our model can describe the QSE trap accurately. With the model, we develop some insights in trap design and find the optimum geometry design for QSE traps as α = 0.15, β = 1.2, and w = a.